ADSP-BF538F View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF538F' PDF : 60 Pages View PDF
ADSP-BF538/ADSP-BF538F
Preliminary Technical Data
External Port Bus Request and Grant Cycle Timing
Table 21 and Table 22 on Page 31 and Figure 16 and Figure 17
on Page 31 describe external port bus request and grant cycle
operations for synchronous and for asynchronous BR.
Table 21. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Parameter
Timing Requirements
tBS
BR Setup to Falling Edge of CLKOUT
tBH
Falling Edge of CLKOUT to BR Deasserted Hold Time
Switching Characteristics
tSD
CLKOUT Low to xMS, Address, and RD/WR disable
tSE
CLKOUT Low to xMS, Address, and RD/WR enable
tDBG
CLKOUT High to BG High Setup
tEBG
CLKOUT High to BG Deasserted Hold Time
tDBH
CLKOUT High to BGH High Setup
tEBH
CLKOUT High to BGH Deasserted Hold Time
Min
Max
Unit
TBD
ns
TBD
ns
4.5
ns
4.5
ns
3.6
ns
3.6
ns
3.6
ns
3.6
ns
CLKOUT
BR
AMSx
ADDR19-1
ABE1-0
AWE
ARE
BG
BGH
tBS
tBH
tSD
tSE
tSD
tSE
tSD
tSE
tDBG
tEBG
tDBH
tEBH
Figure 16. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Rev. PrD | Page 30 of 56 | May 2006
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