Preliminary Technical Data
ADSP-BF538/ADSP-BF538F
Table 38. 316-Ball Mini-BGA Pin Assignment (Alphabetically by Signal)
Signal
ABE0
ABE1
ADDR1
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
AMS0
AMS1
AMS2
AMS3
AOE
ARDY
ARE
AWE
BG
BGH
BMODE0
BMODE1
BR
CANRX
CANTX
CLKIN
CLKOUT
DATA0
DATA1
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal
M19 DATA2 Y9
GND E7
GND K11 GND
M20 DATA3 W9
GND E8
GND K12 GND
N19 DATA4 Y8
GND E9
GND K13 GND
U20 DATA5 W8
GND F8
GND L13 GND
V19 DATA6 Y7
GND F9
GND L14 GND
V20 DATA7 W7
GND F10 GND M3
GND
W18 DATA8 Y6
GND F11 GND M8
GND
W20 DATA9 W6
GND F12 GND M9
GND
W17 DR0PRI N2
GND F13 GND M10 GND
Y19 DR0SEC J3
GND F14 GND M11 GPW
Y18 DR1PRI J2
GND G7
GND M12 MISO0
W16 DR1SEC H3
GND G8
GND M13 MISO1
Y17 DR2PRI W12 GND G9
GND N3
MISO2
N20 DR2SEC V13 GND E10 GND K14 MOSI0
P19 DR3PRI R18 GND E11 GND L3
MOSI1
P20 DR3SEC P18 GND E12 GND L7
MOSI2
R19 DT0PRI M1
GND E13 GND L8
NC
R20 DT0SEC G3
GND E14 GND L9
NMI
T19 DT1PRI H1
GND E18 GND L10 PC4
T20 DT1SEC D3
GND F3
GND L11 PC5
U19 DT2PRI W13 GND F7
GND L12 PC6
J18
DT2SEC V16 GND G10 GND N8
PC7
K19 DT3PRI F18 GND G11 GND N9
PC8
J19
DT3SEC N18 GND G12 GND N10 PC9
K18 EMU T2
GND G13 GND N11 PF0
K20 FCE H18 GND G14 GND N12 PF1
E20 FRESET Y14 GND H7
GND N13 PF10
L19 GND A1
GND H8
GND P3
PF11
L20 GND A12 GND H9
GND P8
PF12
V14 GND A20 GND H10 GND P9
PF13
V15 GND B2
GND H11 GND P10 PF14
V5
GND B18 GND H12 GND P11 PF15
V4
GND B19 GND H13 GND P12 PF2
G18 GND C3
GND H14 GND P13 PF3
B11 GND C4
GND J7
GND R3
PF4
B12 GND C18 GND J8
GND R8
PF5
A13 GND D7
GND J9
GND R9
PF6
G19 GND D8
GND J10
GND R10
PF7
Y10 GND D9
GND J11
GND R11
PF8
W10 GND D10 GND J12
GND R12
PF9
Y5
GND D11 GND J13
GND R13
PPI_CLK
W5
GND D12 GND J14
GND T3
PPI0
Y4
GND D13 GND K7
GND U3
PPI1
W4
GND D14 GND K8
GND V2
PPI2
Y3
GND D18 GND K9
GND V3
PPI3
W3
GND E3
GND K10 GND V6
RESET
Ball No. Signal Ball No. Signal Ball No.
V17 RFS0 P2
TX0
R1
V18 RFS1 K1
TX1
C6
W2
RFS2 Y11 TX2
W15
W19 RFS3 T18 VDDEXT K3
Y1
RSCK0 R2
VDDEXT B15
Y20 RSCK1 L1
VDDEXT T8
A15 RSCK2 W11 VDDEXT T9
B16 RSCK3 U18 VDDEXT T10
A17 RTXI A11 VDDEXT T11
A18 RTXO A10 VDDEXT U7
F2
RX0 T1
VDDEXT U8
C14 RX1 C5
VDDEXT U9
C10 RX2 W14 VDDEXT U10
G2
SA10 J20
VDDEXT U11
C16 SCAS H19 VDDEXT V7
C9
SCK0 G1
VDDEXT M7
A16 SCK1 C17 VDDEXT N7
B13 SCK2 C11 VDDEXT P7
F19 SCKE C20 VDDEXT R7
E19 SCL0 B9
VDDEXT T7
C19 SCL1 Y15 VDDEXT V8
D19 SDA0 B10 VDDEXT V9
F20 SDA1 Y16 VDDEXT V10
C17 SMS D20 VDDEXT V11
F1
SPI1SEL C13 VDDINT C12
E1
SPI1SS C15 VDDINT M14
A2
SPI2SEL C7
VDDINT N14
A3
SPI2SS C8
VDDINT P14
B8
SRAS G20 VDDINT R14
A8
SWE H20 VDDINT T12
B7
TCK W1
VDDINT T13
A7
TDI V1
VDDINT T14
E2
TDO Y2
VDDINT U12
B4
TFS0 N1
VDDINT U13
D1
TFS1 J1
VDDINT U14
D2
TFS2 Y13 VDDINT V12
C1
TFS3 M18 VDDRTC A9
C2
TMR0 M2
VROUT0 B20
B1
TMR1 L2
VROUT1 A19
B3
TMR2 K2
XTAL A14
A4
TMS U2
A5
TRST U1
B5
TSCK0 P1
A6
TSCK1 H2
B6
TSCK2 Y12
B14 TSCK3 L18
Rev. PrD | Page 53 of 56 | May 2006