ADSP-BF539F View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF539F' PDF : 60 Pages View PDF
Preliminary Technical Data
Serial Peripheral Interface (SPI) Ports
—Slave Timing
Table 30 and Figure 27 describe SPI ports slave operations.
Table 30. Serial Peripheral Interface (SPI) Ports—Slave Timing
Parameter
Timing Requirements
tSPICHS
Serial Clock High Period
tSPICLS
Serial Clock low Period
tSPICLK
Serial Clock Period
tHDS
Last SCK Edge to SPIxSS Not Asserted
tSPITDS
Sequential Transfer Delay
tSDSCI
SPIxSS Assertion to First SCK Edge
tSSPID
Data Input Valid to SCK Edge (Data Input Setup)
tHSPID
SCK Sampling Edge to Data Input Invalid
Switching Characteristics
tDSOE
tDSDHI
tDDSPID
tHDSPID
SPIxSS Assertion to Data Out Active
SPIxSS Deassertion to Data High impedance
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
ADSP-BF539/ADSP-BF539F
Min
Max
2tSCLK – 1.5
2tSCLK – 1.5
4tSCLK – 1.5
2tSCLK – 1.5
2tSCLK – 1.5
2tSCLK – 1.5
1.6
1.6
0
8
0
8
0
10
0
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPIxSS
(INPUT)
SCKx
(CPOL = 0)
(INPUT)
SCKx
(CPOL = 1)
(INPUT)
MISOx
(OUTPUT)
tSPICHS
tSPICLS
tSDSCI
tSPICLS
tSPICHS
tDSOE
tDDSPID
tHDSPID
MSB
CPHA=1
MOSIx
(INPUT)
tSSPID
tHSPID
MSB VALID
tDSOE
tDDSPID
MISOx
(OUTPUT)
MSB
CPHA=0
MOSIx
(INPUT)
MSB VALID
tSPICLK
tHDS
tSPITDS
tDDSPID
tSSPID
tDSDHI
LSB
tHSPID
LSB VALID
tDSDHI
LSB
tSSPID
tHSPID
LSB VALID
Figure 27. Serial Peripheral Interface (SPI) Ports—Slave Timing
Rev. PrF | Page 49 of 68 | September 2006
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