ADSP-BF539F View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF539F' PDF : 60 Pages View PDF
ADSP-BF539/ADSP-BF539F
Preliminary Technical Data
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 44). VLOAD is 1.5 V for VDDEXT
(nominal) = 2.5/3.3 V. Figure 45 on Page 58 through Figure 54
on Page 59 show how output rise time varies with capacitance.
The delay and hold specifications given should be de-rated by a
factor derived from these figures. The graphs in these figures
may not be linear outside the ranges shown.
ABE0 (133 MHz DRIVER), VDDEXT (MIN) = 2.7V
14
12
RISE TIME
10
FALL TIME
8
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 45. Typical Rise and Fall Times (10%–90%) versus Load Capacitance
for Driver A at VDDEXT (min)
ABE0 (133 MHz DRIVER), VDDEXT (MAX) = 3.65V
12
10
RISE TIME
8
FALL TIME
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 46. Typical Rise and Fall Times (10%–90%) versus Load Capacitance
for Driver A at VDDEXT (max)
CLKOUT (CLKOUT DRIVER), VDDEXT (MIN) = 2.7V
12
10
RISE TIME
8
FALL TIME
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 47. Typical Rise and Fall Times (10%–90%) versus Load Capacitance
for Driver B at VDDEXT (min)
CLKOUT (CLKOUT DRIVER), VDDEXT (MAX) = 3.65V
10
9
8
RISE TIME
7
6
FALL TIME
5
4
3
2
1
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 48. Typical Rise and Fall Times (10%–90%) versus Load Capacitance
for Driver B at VDDEXT (max)
30
PF9 (33 MHz DRIVER), VDDEXT (MIN) = 2.7V
25
RISE TIME
20
15
FALL TIME
10
5
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 49. Typical Rise and Fall Times (10%–90%) versus Load Capacitance
for Driver C at VDDEXT (min)
Rev. PrF | Page 58 of 68 | September 2006
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