ADSP-BF539WBBCZ-5A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF539WBBCZ-5A' PDF : 68 Pages View PDF
Preliminary Technical Data
Parallel Peripheral Interface Timing
Table 24 and Figure 19, Figure 20, Figure 21, and Figure 22
describe Parallel Peripheral Interface operations.
Table 24. Parallel Peripheral Interface Timing
Parameter
Timing Requirements
tPCLKW
PPI_CLK Width
tPCLK
PPI_CLK Period1
tSFSPE
External Frame Sync Setup Before PPI_CLK
tHFSPE
External Frame Sync Hold After PPI_CLK
tSDRPE
Receive Data Setup Before PPI_CLK
tHDRPE
Receive Data Hold After PPI_CLK
Switching Characteristics — GP Output and Frame Capture Modes
tDFSPE
tHOFSPE
tDDTPE
tHDTPE
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
1 PPI_CLK frequency cannot exceed fSCLK/2
POLC = 0
PPI_CLK
PPI_CLK
POLC = 1
POLS = 1
PPI_FS1
POLS = 0
FRAME
SYNC IS
DRIVEN
OUT
DATA0
IS
SAMPLED
tDFSPE
tHOFSPE
ADSP-BF539/ADSP-BF539F
Min
Max
Unit
6.0
ns
15.0
ns
5.0
ns
1.0
ns
2.0
ns
4.0
ns
10.0
ns
0.0
ns
10.0
ns
0.0
ns
POLS = 1
PPI_FS2
POLS = 0
PPI_DATA
tSDRPE
tHDRPE
Figure 19. PPI GP Rx Mode with Internal Frame Sync Timing
Rev. PrF | Page 41 of 68 | September 2006
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