ADSP-BF539WBBCZ-5A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF539WBBCZ-5A' PDF : 68 Pages View PDF
Preliminary Technical Data
ADSP-BF539/ADSP-BF539F
Clock and Reset Timing
Table 16 and Figure 11 describe clock and reset operations. Per
Absolute Maximum Ratings on Page 29, combinations of
CLKIN and clock multipliers must not select core/peripheral
clocks in excess of 500/133 MHz.
Table 16. Clock and Reset Timing
Parameter
Minimum
Maximum
Unit
Timing Requirements
tCKIN
tCKINL
tCKINH
tWRST
CLKIN Period
CLKIN Low Pulse1
CLKIN High Pulse1
RESET Asserted Pulsewidth Low2
20.0
100.0
ns
8.0
ns
8.0
ns
11 tCKIN
ns
1 Applies to bypass mode and non-bypass mode.
2 Applies after power-up sequence is complete. At power-up, the processor’s internal phase locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,
assuming stable power supplies and CLKIN (not including startup time of external clock oscillator).
CLKIN
RESET
tCKIN
tCKINL
tCKINH
tWRST
Figure 11. Clock and Reset Timing
Rev. PrF | Page 31 of 68 | September 2006
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