ADSP-BF539WBBCZ-5A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF539WBBCZ-5A' PDF : 68 Pages View PDF
Preliminary Technical Data
SDRAM Interface Timing
Table 21. SDRAM Interface Timing
Parameter
Timing Requirements
tSSDAT
DATA Setup Before CLKOUT
tHSDAT
DATA Hold After CLKOUT
Switching Characteristics
tSCLK
tSCLKH
tSCLKL
tDCAD
tHCAD
tDSDAT
tENSDAT
CLKOUT Period
CLKOUT Width High
CLKOUT Width Low
Command, ADDR, Data Delay After CLKOUT1
Command, ADDR, Data Hold After CLKOUT2
Data Disable After CLKOUT
Data Enable After CLKOUT
1 Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
2 SDRAM timing for TJUNCTION = 125° C is limited to 100 MHz.
CLKOUT
DATA (IN)
tSSDAT
D ATA(O UT)
ADSP-BF539/ADSP-BF539F
Minimum
Maximum
Unit
2.1
ns
0.8
ns
7.5
ns
2.5
ns
2.5
ns
6.0
ns
0.8
ns
6.0
ns
1.0
ns
tSCLK
tSCLKH
tHSDAT
tSCLKL
tENSDAT
tDCAD
tD SDA T
tHCAD
CMND ADDR
(OUT)
tDCAD
tHCAD
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 16. SDRAM Interface Timing
Rev. PrF | Page 37 of 68 | September 2006
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