ADSP-BF539WBBCZ-5A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF539WBBCZ-5A' PDF : 68 Pages View PDF
ADSP-BF539/ADSP-BF539F
Asynchronous Memory Read Cycle Timing
Table 17 and Table 18 on Page 32 and Figure 12 and Figure 13
on Page 34 describe asynchronous memory read cycle opera-
tions for synchronous and for asynchronous ARDY.
Table 17. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Parameter
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
tHDAT
DATA15–0 Hold After CLKOUT
tSARDY
ARDY Setup Before the Falling Edge of CLKOUT
tHARDY
ARDY Hold After the Falling Edge of CLKOUT
tDO
Output Delay After CLKOUT1
tHO
Output Hold After CLKOUT1
1 Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
Table 18. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
Parameter
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
tHDAT
DATA15–0 Hold After CLKOUT
tDANR
ARDY Negated Delay from AMSx Asserted1
tHAA
ARDY Asserted Hold After ARE Negated
tDO
Output Delay After CLKOUT2
tHO
Output Hold After CLKOUT2
1 S = number of programmed setup cycles, RA = number of programmed read access cycles.
2 Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
Preliminary Technical Data
Min
Max
Unit
2.1
ns
0.8
ns
4.0
ns
0.0
ns
6.0
ns
0.8
ns
Min
Max
Unit
2.1
ns
0.8
ns
(S+RA–2)*tSCLK ns
0.0
ns
6.0
ns
0.8
ns
Rev. PrF | Page 32 of 68 | September 2006
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