ADV7189B
I2C INTERRUPT REGISTER MAP
The following registers are located in Register Access Page 2.
Table 85. Interrupt (Page 2) Register Map Details
Bit
Subaddress Register Bit Description
76543210
0x40
Interrupt
Config 1
INTRQ_OP_SEL[1:0].
Interrupt Drive Level Select
00
01
Register
Access
Page 2
MPU_STIM_INTRQ[1:0].
Manual Interrupt Set Mode
10
11
0
1
Reserved
x
MV_INTRQ_SEL[1:0].
Macrovision Interrupt Select
00
01
10
11
INTRQ_DUR_SEL[1:0].
Interrupt Duration Select
00
01
10
11
0x41
Reserved
xxxxxxxx
0x42
Interrupt SD_LOCK_Q
0
Status 1
1
Read-Only
Register
Access
Page 2
SD_UNLOCK_Q
Reserved
Reserved
Reserved
SD_FR_CHNG_Q
0
1
x
x
x
0
1
MV_PS_CS_Q
0
1
0x43
Interrupt
Clear 1
Write-Only
Register
Access
Page 2
Reserved
SD_LOCK_CLR
SD_UNLOCK_CLR
Reserved
Reserved
Reserved
SD_FR_CHNG_CLR
MV_PS_CS_CLR
Reserved
x
0
1
0
1
0
0
0
0
1
0
1
x
Comments
Open drain
Drive low when active
Drive high when active
Reserved
Manual interrupt mode disabled
Manual interrupt mode enabled
Not used
Reserved
Pseudo sync only
Color stripe only
Pseudo sync or color stripe
3 Xtal periods
15 Xtal periods
63 Xtal periods
Active until cleared
Notes
No change
SD input has caused the
decoder to go from an unlocked
state to a locked state
No change
SD input has caused the
decoder to go from a locked
state to an unlocked state
These bits
can be
cleared or
masked in
Register
0x43 and
Register
0x44,
respectively.
No change
Denotes a change in the free-
run status
No change
Pseudo sync / color striping
detected. See Reg 0x40
MV_INTRQ_SEL[1:0] for
selection
Do not clear
Clears SD_LOCK_Q bit
Do not clear
Clears SD_UNLOCK_Q bit
Not used
Not used
Not used
Do not clear
Clears SD_FR_CHNG_Q bit
Do not clear
Clears MV_PS_CS_Q bit
Not used
Rev. B | Page 68 of 104