Subaddress
0x44
Register
Interrupt
Mask 1
Read/Write
Register
Register
Access
Page 2
Bit Description
SD_LOCK_MSKB
SD_UNLOCK_MSKB
Reserved
Reserved
Reserved
SD_FR_CHNG_MSKB
MV_PS_CS_MSKB
0x45
0x46
Reserved
Interrupt
Status 2
Reserved
CCAPD_Q
Read-Only
Register
Register
Access
Page 2
GEMD_Q
CGMS_CHNGD_Q
WSS_CHNGD_Q
0x47
Reserved
Reserved
Reserved
MPU_STIM_INTRQ_Q
Interrupt
Clear 2
Write-Only
Register
Access
Page 2
CCAPD_CLR
GEMD_CLR
CGMS_CHNGD_CLR
WSS_CHNGD_CLR
Reserved
Reserved
Reserved
MPU_STIM_INTRQ_CLR
ADV7189B
Bit
76543210
0
1
0
1
0
0
0
0
1
0
1
x
xxxxxxxx
0
1
0
1
0
1
0
1
x
x
x
0
1
0
1
0
1
0
1
0
1
x
x
x
0
1
Comments
Masks SD_LOCK_Q bit
Unmasks SD_LOCK_Q bit
Masks SD_UNLOCK_Q bit
Unmasks SD_UNLOCK_Q bit
Not used
Not used
Not used
Masks SD_FR_CHNG_Q bit
Unmasks SD_FR_CHNG_Q bit
Masks MV_PS_CS_Q bit
Unmasks MV_PS_CS_Q bit
Not used
Notes
Closed captioning not detected
in the input video signal
Closed captioning data
detected in the video input
signal
Gemstar data not detected in
the input video signal
Gemstar data detected in the
input video signal
No change detected in CGMS
data in the input video signal
A change is detected in the
CGMS data in the input video
signal
No change detected in WSS
data in the input video signal
A change is detected in the WSS
data in the input video signal
Not used
Not used
Not used
Manual interrupt not set
Manual interrupt set
Do not clear
Clears CCAPD_Q bit
Do not clear
Clears GEMD_Q bit
Do not clear
Clears CGMS_CHNGD_Q bit
Do not clear
Clears WSS_CHNGD_Q bit
Not used
Not used
Not used
Do not clear
Clears MPU_STIM_INTRQ_Q bit
These bits
can be
cleared or
masked by
Register
0x47 and
Register
0x48,
respectively.
Rev. B | Page 69 of 104