AK4516AVF View Datasheet(PDF) - Asahi Kasei Microdevices
Part Name
Description
MFG CO.
'AK4516AVF' PDF : 39 Pages View PDF
ASAHI KASEI
Overflow Status
[AK4516A]
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
D0
08H Overflow Status
ZFIPR ZFIPL ROF2 ROF1 ROF0 LOF2 LOF1 LOF0
R/W
RD RD RD RD RD RD RD RD
RESET
0
0
0
0
0
0
0
0
ZFIPR: Rch IPGA zero crossing detection flag.
ZFIPL: Lch IPGA zero crossing detection flag.
At writing operation by uP, when ZENM is "1", this flag becomes "0" if IPGA value is set
independently for L/R. When each channel does zero crossing or timeout, and then IPGA of
each channel is changed, the flag of each channel becomes "1".
When writing to the same channel is done again under zero crossing waiting before this flag
becomes "1", the timeout counter is not reset. Therefore then, zero crossing timeout period
becomes shorter for the new writing. But if writing is done to the channel which the flag is "1"
when the flag of either Lch or Rch is "0", the timeout counter is reset. In this case, zero
crossing timeout counter restarts from the last writing.
When ZEIP is "0", ZFIPL/ZFIPR always become "1". ZFIPL/ZFIPR always become "1" during
semi-auto mode operation (LMTE="1", RCVE="0") and full-auto mode operation
(LMTE=RCVE="1").
ZFIPR/ZFIRL is "0" during initializing operation after exiting power-down by PD pin.
The completion of the initializing operation can be recognized by confirming these flags are
"1".
These bits are reset on the following any conditions.
• PD pin="L"
In case of PM0="0", these flag become "1".
ROF2-0:
Overflow Flag of Rch
Overflow flag includes 3 bit. Max value of the overflow is held. These bits are reset to
(0, 0, 0) by reading by uP.
These bits are reset on the following any conditions.
• PD pin="L"
• PM1="0"
ROF2 ROF1 ROF0 Threshold
0
0
0
<-12.04dB
0
0
1
-12.04dB≤
0
1
0
-8.52dB≤
0
1
1
-6.02dB≤
1
0
0
-4.08dB≤
1
0
1
-1.80dB≤
1
1
0
-0.00dB≤
Table 7 . Overflow Flag of Rch
M0026-E-00
- 27 -
1998/08
Share Link: 
