AN2125 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'AN2125' PDF : 68 Pages View PDF
uPSD3300 Series Design Guide for DK3300-ELCD Using KEIL
The 8032 outputs a repetitive PWM pulse train with a slowly varying pulse-width to an RC net-
work which converts the pulse train into a slowly sweeping DC voltage (0V to 3.3V). This DC
signal is looped back into an ADC input. The 8032 will write the resulting HEX ADC conversion
value to the LCD so you can watch the results. The RC network and loop back is implemented
with two jumper blocks (JP14 and JP15) on the DK3300-ELCD board.
Additionally and independently, a 4-bit, auto-reloading down-counter is created using PLD Mi-
croCells. The 8032 directly loads the initial count value into four MicroCells, and that count is
automatically loaded into another four MicroCells that create the 4-bit down-counter. Reload-
ing occurs each time the counter reaches the terminal count of zero. Terminal count is indicat-
ed externally by a pulse on a Turbo uPSD output pin. The down-counter is clocked by an ALE
signal (although in this example ALE was a random choice, it could be any signal). The 8032
may load a different initial count at anytime, creating a variable divider of the ALE signal.
The Graphic LCD module (ELCD) is connected to the Turbo uPSD3334 via Port A for data and
Port B for some glue logic and chip-select signals. Port A operates in a special data bus re-
peater mode for this example, called Peripheral I/O mode. MCU8032 data will pass through
Port A only for a given address range. The details for entering into PSDsoft and the equations
used are described later into this document. (Refer to AN2028 Application Note for further de-
tails of the Graphic LCD Driver and the Hardware Interface with Turbo uPSD.).
Figure 19. Design Example Memory Map
FFFF
Code Space
Page 0 Page 1 Page 2 Page 3 Page 4 Page 5 Page 6
fs1 fs2 fs3 fs4 fs5 fs6 fs7
32 K
bytes
32 K
bytes
32 K
bytes
32 K
bytes
32 K
bytes
32 K
bytes
32 K
bytes
Main
Flash
8000
7FFF
0000
Main
Flash
Main
Flash
Main
Flash
Main
Flash
fs0
32 Kbytes
Main Flash
Main
Flash
Main
Flash
X Data
FFFF
csboot3
8 Kbytes
Secondary Flash
csboot2
8 Kbytes
Secondary Flash
csboot1
8 Kbytes
E000
DFFF
C000
BFFF
Secondary Flash
csboot0
8 Kbytes
A000
9FFF
Secondary Flash
CSIOP
control regs for ports
A,B,C,D
LCD_E1, LCD_E2 and psel0
chip select and databus repeater ELCD
8000
7F00-7FFF
7E00-7EFF
rs0 8K PSD SRAM (xdata) 0000-1FFF
The memory map in Figure 19 shows that in this design example, 32K byte secondary flash
memory is used for Xdata space, and the 256K byte main flash memory is mapped into the
Code space with fs1-fs7, banked over 7 pages. The nomenclature fsx, csbootx, rs0, csiop, and
psel in Figure 19 refer to the individual internal Turbo uPSD memory segments. The Turbo
uPSD main flash memory has a total of eight 32 Kbyte segments (fs0..fs7) (256Kbyte-Total).
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