uPSD3300 Series Design Guide for DK3300-ELCD Using KEIL
The Turbo uPSD secondary Flash memory has a total of four 8 Kbyte segments (csboot0 -
csboot3). All segments are being used in the example code supplied for this design. The Turbo
uPSD 8 Kbyte SRAM has a single segment (rs0). A group of uPSD control registers which con-
trol I/O ports A, B, C, and D lie in a 256-byte xdata address space whose base address is
named csiop. The Turbo uPSD has a data bus repeater feature that is enabled over a given
address range as specified by psel. Figure 18 also shows external memory select signals
(LCD_E1 and LCD_E2) required by the ELCD Module. This memory map is specified using
the software tool PSDsoft Express. Each memory segment can be placed at virtually any ad-
dress, which provides an infinite number of mapping schemes. In a later section all the equa-
tions used are listed and the mapping for the various signals as used by PSDsoft. The key
PSDsoft screens are shown and explained for this example.
For simplicity in this particular application note, the 8032 will "boot" and run code contained
completely within the 32 Kbyte main flash segment in Code space (fs0) and the 256 Kbyte
main flash is treated as Code space paged into multiple pages. The font code required resides
is in secondary flash segment csboot3 of the xdata mapped memory space. However, you can
define alternate memory maps to meet the needs of your particular project. The uPSD memory
space can be re-configured to use the secondary as Code space and the primary 256KB flash
as Xdata space. (Refer to Turbo uPSD Datasheets and related documentation for further de-
tails).
A special register, called the VM Register within the csiop register block, is used to "reclassify"
the main flash memory from code space to data space. The VM Register can be accessed by
the 8032 at runtime to perform a variety of manipulations. PSDsoft is used to set the initial val-
ue of the VM Register upon power-up.
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