uPSD3300 Series Design Guide for DK3300-ELCD Using KEIL
Figure 26. Pin definitions for Port B (Pins 3-4)
Walk through some of the pins to verify each pin definitions and get an overview of the design
implementation.
Click "Next" in step-3 (final step) to move on to the Design Assistant for memory mapping and
logic equations. You will see the Design Assistant Screen with the following tabs:
■ Page Register definition
■ Chip Select Equations
■ I/O Logic Equations
■ User-defined Node Equations
This is a key part of the design process and requires careful entry for the pin definitions and
associated memory maps and logic equations. Since this determines how PSDsoft maps the
memory Address space and makes the PLD connections it is imperative that the memory map
matches the chip selects for individual memory elements of the Turbo uPSD (memory external
to the 8032 core). Definition of the use of the Turbo uPSD Page Register is also required.
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