AN2125 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'AN2125' PDF : 68 Pages View PDF
uPSD3300 Series Design Guide for DK3300-ELCD Using KEIL
Four memory blocks (Main flash, Secondary flash, SRAM, and Control Registers) external to
the 8032 core are available and are individually selected segment-by-segment when 8032 ad-
dresses are presented to the Decode PLD (DPLD). Each of these memory segments has its
own chip-select name (fs0, fs1.. csboot1, rs0, csiop, and so forth). Equations for these chip-
selects, and for any external chip-selects, must be specified using PSDsoft Express. For this
example, chip-selects are defined to match the memory map.
7.2 Page Register
Paging bits may be used for other types of memory manipulation (such as memory swapping),
but that will be discussed in other application notes.
Select this bit for memory paging. Use one bit to define two memory pages, use two bits to
define four pages, three bits for eight pages and so on. Select enough bits to cover the number
required pages. Always start with pgr0 and add more bits going upward, as these bits are an
extension of the MCU's or DSP's natural address bits.
The MCU/DSP reads and writes the PSD page register bits at run-time to control the system
memory map. Outputs of the page register feed the inputs to both PLDs within the PSD.
Since eight memory pages (or banks) are needed as shown in the memory map diagram of
the design (Figure 19), three paging bits (23 = 8) are specified in the Screen below (Figure 27)
Figure 27. Page Register Definitions
38/68
1
Share Link: 
