AN2125 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'AN2125' PDF : 68 Pages View PDF
uPSD3300 Series Design Guide for DK3300-ELCD Using KEIL
APPENDIX C. PSDSOFT REPORTS
Project.frp
This report is generated by PSDsoft after the Fit design to silicon step and the report for this
example is listed here. Some Key points are highlighted for reviewing in relationship to the ex-
ample design.
******************************************************************************************
PSDsoft Express Version 8.30
Output of PSD Fitter
******************************************************************************************
PROJECT : project
DATE : 01/18/2005
DEVICE : uPSD3334D
TIME : 17:56:54
FIT OPTION : Keep Current
DESCRIPTION: Combo Demo code to demonstrate Turbo uPSD's IPs: PCA-PWM,
I2C, SPI, and JTAG, it runs on a DK3300 ELCD board.
******************************************************************************************
==== Pin Layout for U (80-Pin TQFP) Package Type ====
-----------------------------
|
|
pd2 |1 ] pd2
adio4 [41| Address Bus a4/Data Port d4, ad4
|2 ] p3_3
p3_5 [42|
pd1 |3 ] pd1
adio5 [43| Address Bus a5/Data Port d5, ad5
ale |4 ] pd0
p3_6 [44|
|5 ] pc7
adio6 [45| Address Bus a6/Data Port d6, ad6
tdo, TDO |6 ] pc6/TDO
p3_7 [46|
tdi, TDI |7 ] pc5/TDI
adio7 [47| Address Bus a7/Data Port d7, ad7
JTAG_debug_pin |8 ] debug
Xtal1 [48| Xtal1
_terr, TERR |9 ] pc4/TERR
Xtal2 [49| Xtal2
|10] 3.3V VCC 5.0V VCC [50|
|11] N/C
adio8 [51| Address Bus a8, a8
|12] 5.0V VCC
p1_0 [52|
|13] GND
adio9 [53| Address Bus a9, a9
tstat, TSTAT |14] pc3/TSTAT
p1_1 [54|
|15] pc2
adio10 [55| Address Bus a10, a10
tck, TCK |16] pc1/TCK
p1_2 [56|
|17] N/C
adio11 [57| Address Bus a11, a11
|18] p4_7
p1_3 [58|
|19] p4_6
p1_4 [59|
tms, TMS |20] pc0/TMS
p1_5 [60|
pa7 ,Peripheral I/O Mode |21] pa7
p1_6 [61|
pa6 ,Peripheral I/O Mode |22] pa6
cntl0 [62| _wr
|23] p4_5
cntl2 [63| _psen
pa5 ,Peripheral I/O Mode |24] pa5
p1_7 [64|
|25] p4_4
cntl1 [65| _rd
pa4 ,Peripheral I/O Mode |26] pa4
pb7 [66| pb7
|27] p4_3
pb6 [67| En_EA
pa3 ,Peripheral I/O Mode |28] pa3
Reset_In [68| _Reset_In
|29] GND
GND [69|
|30] p4_2
Vref [70| VREF
|31] p4_1
pb5 [71| En_EB
pa2 ,Peripheral I/O Mode |32] pa2
AVcc [72|
|33] p4_0
pb4 [73| LCD_E2
pa1 ,Peripheral I/O Mode |34] pa1
pb3 [74| LCD_E1
pa0 ,Peripheral I/O Mode |35] pa0
p3_0 [75|
ad0, Address Bus a0/Data Port d0 |36] adio0
pb2 [76| LCD_RW
ad1, Address Bus a1/Data Port d1 |37] adio1
p3_1 [77|
ad2, Address Bus a2/Data Port d2 |38] adio2
pb1 [78| LCD_A0
ad3, Address Bus a3/Data Port d3 |39] adio3
p3_2 [79|
|40] p3_4
pb0 [80|
|
|
-----------------------------
==== Global Configuration ====
Data Bus
: 8-Bit
Address/Data Mode
: Multiplexed
ALE/AS Signal
: Active High
Control Signals
: /WR, /RD, /PSEN
Main PSD flash memory will reside in this space at power-up
: Program space
Secondary PSD flash memory will reside in this space at power-up : Data space
Enable Chip-Select Input(/CSI)
: OFF
Standby Voltage Input (PC2)
: OFF
Standby-on Indicator (PC4)
: OFF
RDY/Busy function (PC3)
: OFF
Load Micro-Cell on
: edge
Security Protection
: OFF
==== DataBus_IMC access information ====
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