APW7065C View Datasheet(PDF) - Anpec Electronics
Part Name
Description
MFG CO.
'APW7065C' PDF : 19 Pages View PDF
APW7065C
Application Information (Cont.)
MOSFET Selection (Cont.)
tSW is the switching interval
D is the duty cycle
FLC
-40dB/dec
Note that both MOSFETs have conduction loss while the
upper MOSFET, including an additional transition loss.
The switching internal, t , is a function of the reverse
SW
transfer capacitance CRSS. The (1+TC) term is to factor in
the temperature dependency of the RDS(ON) and can be
extracted from the “R vs. Temperature” curve of the
DS(ON)
power MOSFET.
FESR
-20dB/dec
Frequency(Hz)
Figure 4. The LC Filter GAIN and Frequency
PWM Compensation
The output LC filter of a step down converter introduces a
double pole, which contributes with -40dB/decade gain
slope and 180 degrees phase shift in the control loop. A
compensation network among COMP, FB and V should
OUT
be added. The compensation network is shown in Fig-
ure 6. The output LC filter consists of the output inductor
and output capacitors. The transfer function of the LC
filter is given by:
The PWM modulator is shown in Figure 5. The input is
the output of the error amplifier and the output is the
PHASE node. The transfer function of the PWM modu-
lator is given by:
GAINPWM
=
VIN
∆VOSC
VIN
Driver
OSC
ΔVOSC
PWM
Comparator
GAINLC
=
s2
1+ s × ESR × COUT
× L × COUT + s × ESR × COUT
+1
The poles and zero of this transfer functions are:
FLC = 2 × π ×
1
L × COUT
FESR
=
1
2 × π × ESR × COUT
The FLC is the double poles of the LC filter, and FESR is the
zero introduced by the ESR of the output capacitor.
PHASE
L
OUTPUT
COUT
Output of Error
Amplifier
PHASE
Driver
Figure 5. The PWM Modulator
The compensation network is shown in Figure 6. It
provides a close loop transfer function with the highest
zero crossover frequency and sufficient phase margin.
The transfer function of error amplifier is given by:
1 //R2 + 1
GAINAMP
=
VCOMP
VOUT
=
sC1
R1//R3 +
sC2
1
sC3
ESR
Figure 3. The Output LC Filter
=
R1+ R3
×
s
+
R2
1
×
C2
×
s
+
(R1+
1
R3)×
C3
R1× R3 × C1
s
s
+
C1+ C2
R2 × C1× C2
×
s
+
R3
1
×
C3
Copyright © ANPEC Electronics Corp.
13
Rev. A.2 - Mar., 2008
www.anpec.com.tw
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