APW7065C View Datasheet(PDF) - Anpec Electronics
Part Name
Description
MFG CO.
'APW7065C' PDF : 19 Pages View PDF
APW7065C
Application Information (Cont.)
PWM Compensation (Cont.)
FZ1 FZ2 FP1 FP2
20log
(R2/R1)
Compensation
20log
Gain
(VIN/ΔVOSC)
FLC
FESR
PWM & Filter Gain
Frequency(Hz)
Converter Gain
Figure 7. Converter Gain and Frequency
Layout Consideration
In any high switching frequency converter, a correct lay-
out is important to ensure proper operation of the
regulator. With power devices switching at 300kHz,the
resulting current transient will cause voltage spike across
the interconnecting impedance and parasitic circuit
elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off, the MOSFET is car-
rying the full load current. During turn-off, current stops
flowing in the MOSFET and is free-wheeling by the lower
MOSFET and parasitic diode. Any parasitic inductance of
the circuit generates a large voltage spike during the
switching interval. In general, using short, wide printed
circuit traces should minimize interconnecting im-
pedances and the magnitude of voltage spike. In addtion,
signal and power grounds are to be kept separate till
combined using ground plane construction or single point
grounding. Figure 8. illustrates the layout, with bold lines
indicating high current paths; these traces must be short
and wide. Components along the bold lines should be
placed lose together. Below is a checklist for your layout:
- Keep the switching nodes (UGATE, LGATE and
PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals. Therefore,
keep traces to these nodes as short as possible.
- The traces from the gate drivers to the MOSFETs
(UG, LG) should be short and wide.
- Place the source of the high-side MOSFET and the
drain of the low-side MOSFET as close as possible.
Minimizing the impedance with wide layout plane
between the two pads reduces the voltage bounce of
the node.
- Decoupling capacitor, compensation component,
the resistor dividers, and boot capacitors should
be close their pins. (For example, place the
decoupling ceramic capacitor near the drain of the
high-side MOSFET as close as possible. The bulk
capacitors are also placed near the drain).
- The input capacitor should be near the drain of the
upper MOSFET; the output capacitor should be near
the loads. The input capacitor GND should be close
to the output capacitor GND and the lower MOSFET
GND.
- The drain of the MOSFETs (VIN and PHASE nodes)
should be a large plane for heat sinking.
APW7065C
VCC
BOOT
UGATE
PHASE
LGATE
VIN
L
O
A
D
VOUT
Figure 8. Layout Guidelines
Copyright © ANPEC Electronics Corp.
15
Rev. A.2 - Mar., 2008
www.anpec.com.tw
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