AS4LC4M16S0
AS4LC16M4S0
®
Interleaved bank read waveform
CLK
tRC
CS
RAS
tRAS
CAS
(BL = 8, CL = 3, Autoprecharge)
tRC
tRP
tRAS
tRAS
tRP
WE
BA0/BA1† Bank
A10
RAa
Bank
tRCD
Bank
tRCD
RBb
Bank
Bank
RAc
A0–A9, A11 RAa
CAa
DQM
CKE
RBb
CAb
RAc
DQ
QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBb0 QBb1
tRRD
tRRD
Bank A Active
Bank B
Read
AP
Active
Read
Active
† BA0 and BA1 together determine which bank undergoes operations. AP = internal precharge begins.
Bank
tRCD
CAc
QBb4 QBb5 QBb6 QAc0
QAc0
Read AP
Interleaved bank write waveform
(BL = 8)
CLK
CS
RAS
CAS
WE
BA0/BA1† Bank
tRCD
Bank
tRC
tRAS
tRCD
Bank
Bank
tRP
tRAS
tRCD
Bank
Bank
A10
RAa
A0-A9,A11 RAa
CAa
DQM
CKE
RBb
RBb
CAb
RAc
RAc
CAc
DQ
DAa0 DAa1
DAa4 DAa5 DAa6 DAa7 DBb0 DBb1 DBb2 DBb3
Bank A Active
Bank B
Write
Active
† BA0 and BA1 together determine which bank undergoes operations.
Write Precharge
DBb4 DBb5 DBb6 DBb7 DAc0 DAc1 DAc2
Active
Write Precharge
22
ALLIANCE SEMICONDUCTOR
7/5/00