Table 5. AC Characteristics
Applicable over recommended operating range from TA = –40⋅C to +125⋅C, VCC = +2.5V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
AT34C02C
Symbol
Parameter
Min
Max
Units
fSCL
tLOW
tHIGH
tI
tAA
tBUF
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
tF
tSU.STO
tDH
tWR
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time(1)
Clock Low to Data Out Valid
Time the bus must be free before a new
transmission can start(1)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
Endurance(1) 25⋅C, Page Mode
Note: 1. This parameter is ensured by characterization only.
400
kHz
1.2
µs
0.6
µs
50
ns
0.1
0.9
µs
1.2
µs
0.6
µs
0.6
µs
0
µs
100
ns
300
ns
300
ns
0.6
µs
50
ns
5
ms
1M
Write
Cycles
Memory
Organization
AT34C02C, 2K Serial EEPROM: The 2K is internally organized with 16 pages of 16 bytes each.
Random word addressing requires a 8-bit data word address.
Device
Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on
page 6). Data changes during SCL high periods will indicate a start or stop condition as defined
below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see Figure 5 on page 6).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-
ure 5 on page 6).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each
word. This happens during the ninth clock cycle.
4 AT34C02C
5242B–SEEPR–01/09