AT34C02C
STANDBY MODE: The AT34C02C features a low-power standby mode which is enabled: (a)
upon power-up or (b) after the receipt of the STOP bit and the completion of any internal
operations.
2-WIRE SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any
2-wire part can be protocol reset by following these steps (a) Create a start bit condition, (b)
Clock 9 cycles, (c) Create another start bit followed by a stop bit condition as shown below. The
device is ready for next communication after above steps have been completed.
Start Bit
Dummy Clock Cycles
Start Bit
SCL
1
2
3
8
9
Stop Bit
SDA
Figure 2. Bus Timing SCL: Serial Clock SDA: Serial Data I/O
Figure 3. Write Cycle Timing SCL: Serial Clock SDA: Serial Data I/O
SCL
SDA
8th BIT
WORDn
ACK
STOP
CONDITION
(1)
twr
START
CONDITION
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
5
5242B–SEEPR–01/09