AT45DB041B View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT45DB041B' PDF : 33 Pages View PDF
6. Power-on/Reset State
When power is first applied to the device, or when recovering from a reset condition, the device
will default to SPI Mode 3. In addition, the SO pin will be in a high-impedance state, and a high-
to-low transition on the CS pin will be required to start a valid instruction. The SPI mode will be
automatically selected on every falling edge of CS by sampling the inactive clock state. After
power is applied and VCC is at the minimum datasheet value, the system should wait 20 ms
before an operational mode is started.
Table 6-1. Detailed Bit-level Addressing Sequence
Address Byte
Address Byte
Address Byte
Opcode
Opcode
Additional
Don’t Care
Bytes
Required
50H 0 1 0 1 0 0 0 0 r r r r P P P P P P P P x x x x x x x x x x x x
N/A
52H 0 1 0 1 0 0 1 0 r r r r P P P P P P P P P P P B B B B B B B B B 4 Bytes
53H 0 1 0 1 0 0 1 1 r r r r P P P P P P P P P P P x x x x x x x x x
N/A
54H 0 1 0 1 0 1 0 0 x x x x x x x x x x x x x x x B B B B B B B B B 1 Byte
55H 0 1 0 1 0 1 0 1 r r r r P P P P P P P P P P P x x x x x x x x x
N/A
56H 0 1 0 1 0 1 1 0 x x x x x x x x x x x x x x x B B B B B B B B B 1 Byte
57H 0 1 0 1 0 1 1 1
N/A
N/A
N/A
N/A
58H 0 1 0 1 1 0 0 0 r r r r P P P P P P P P P P P x x x x x x x x x
N/A
59H 0 1 0 1 1 0 0 1 r r r r P P P P P P P P P P P x x x x x x x x x
N/A
60H 0 1 1 0 0 0 0 0 r r r r P P P P P P P P P P P x x x x x x x x x
N/A
61H 0 1 1 0 0 0 0 1 r r r r P P P P P P P P P P P x x x x x x x x x
N/A
68H 0 1 1 0 1 0 0 0 r r r r P P P P P P P P P P P B B B B B B B B B 4 Bytes
81H 1 0 0 0 0 0 0 1 r r r r P P P P P P P P P P P x x x x x x x x x
N/A
82H 1 0 0 0 0 0 1 0 r r r r P P P P P P P P P P P B B B B B B B B B
N/A
83H 1 0 0 0 0 0 1 1 r r r r P P P P P P P P P P P x x x x x x x x x
N/A
84H 1 0 0 0 0 1 0 0 x x x x x x x x x x x x x x x B B B B B B B B B
N/A
85H 1 0 0 0 0 1 0 1 r r r r P P P P P P P P P P P B B B B B B B B B
N/A
86H 1 0 0 0 0 1 1 0 r r r r P P P P P P P P P P P x x x x x x x x x
N/A
87H 1 0 0 0 0 1 1 1 x x x x x x x x x x x x x x x B B B B B B B B B
N/A
88H 1 0 0 0 1 0 0 0 r r r r P P P P P P P P P P P x x x x x x x x x
N/A
89H 1 0 0 0 1 0 0 1 r r r r P P P P P P P P P P P x x x x x x x x x
N/A
D2H 1 1 0 1 0 0 1 0 r r r r P P P P P P P P P P P B B B B B B B B B 4 Bytes
D4H 1 1 0 1 0 1 0 0 x x x x x x x x x x x x x x x B B B B B B B B B 1 Byte
D6H 1 1 0 1 0 1 1 0 x x x x x x x x x x x x x x x B B B B B B B B B 1 Byte
D7H 1 1 0 1 0 1 1 1
N/A
N/A
N/A
N/A
E8H 1 1 1 0 1 0 0 0 r r r r P P P P P P P P P P P B B B B B B B B B
Note:
r = Reserved Bit
P = Page Address Bit
B = Byte/Buffer Address Bit
x = Don’t Care
4 Bytes
12 AT45DB041B
3443C–DFLSH–5/05
Share Link: 
