AT45DB041B View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT45DB041B' PDF : 33 Pages View PDF
AT45DB041B
11. AC Waveforms
Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low
when CS makes a high-to-low transition, and Waveform 2 shows the SCK signal being high
when CS makes a high-to-low transition. Both waveforms show valid timing diagrams. The setup
and hold times for the SI signal are referenced to the low-to-high transition on the SCK signal.
Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows tim-
ing that is compatible with SPI Mode 3.
11.1 Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0
tCS
CS
SCK
tCSS
tWH
tWL
tCSH
tV
HIGH IMPEDANCE
SO
tHO
VALID OUT
tDIS
HIGH IMPEDANCE
tSU
tH
SI
VALID IN
11.2 Waveform 2 – Inactive Clock Polarity High and SPI Mode 3
tCS
CS
SCK
tCSS
tWL
tWH
tCSH
tV
HIGH Z
SO
tHO
VALID OUT
tDIS
HIGH IMPEDANCE
tSU
tH
SI
VALID IN
11.3 Reset Timing (Inactive Clock Polarity Low Shown)
CS
SCK
RESET
SO
HIGH IMPEDANCE
tREC
tRST
tCSS
HIGH IMPEDANCE
SI
Note: The CS signal should be in the high state before the RESET signal is deasserted.
15
3443C–DFLSH–5/05
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