AT45DB080-TC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT45DB080-TC' PDF : 18 Pages View PDF
AT45DB080
AC Waveforms
Two different timing diagrams are shown below. Waveform
1 shows the CLK signal being low when CS makes a high-
to-low transition, and Waveform 2 shows the CLK signal
being high when CS makes a high-to-low transition. Both
waveforms show valid timing diagrams. The setup and hold
times for the SI signal are referenced to the low-to-high
transition on the CLK signal.
Waveform 1 – Inactive Clock Polarity Low
tCS
CS
tCSS
tWH tWL
tCSH
CLK
I/O7-I/O0
(OUTPUT)
I/O7-I/O0
(INPUT)
tV
HIGH IMPEDANCE
tSU
tH
VALID IN
tHO
VALID OUT
tDIS
HIGH IMPEDANCE
Waveform 2 – Inactive Clock Polarity High
CS
CLK
I/O7-I/O0
(OUTPUT)
I/O7-I/O0
(INPUT)
tCSS tWL tWH
tV
HIGH Z
tSU
tHO
VALID OUT
tH
VALID IN
tCSH
tCS
tDIS
HIGH IMPEDANCE
7
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