AT45DB321C View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT45DB321C' PDF : 40 Pages View PDF
AT45DB321C
11. Input Test Waveforms and Measurement Levels
AC
3.0V
DRIVING
LEVELS 0V
tR, tF < 2 ns (10% to 90%)
1.5V
AC
MEASUREMENT
LEVEL
12. Output Test Load
DEVICE
UNDER
TEST
30 pF
13. AC Waveforms
Four different timing waveforms are shown below. Waveform 1 shows the SCK signal being low
when CS makes a high-to-low transition, and waveform 2 shows the SCK signal being high
when CS makes a high-to-low transition. In both cases, output SO becomes valid while the SCK
signal is still low (SCK low time is specified as tWL). Timing waveforms 1 and 2 conform to Rap-
idS serial interface but for frequencies up to 33 MHz and are compatible with SPI Mode 0 and
SPI Mode 3 respectively. Waveforms 1 and 2 are also compatible with inactive clock polarity low
and inactive clock polarity high, since the maximum specified frequency in that case is 33 MHz.
Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial interface. These
are similar to waveform 1 and waveform 2, except that output SO is not restricted to become
valid during the tWL period. These timing waveforms are valid over the full frequency range (max-
imum frequency = 40 MHz) of the RapidS serial case.
13.1 Waveform 1 – SPI Mode 0 Compatible (for Frequencies up to 33 MHz)
tCS
CS
SCK
tCSS
tWH
tWL
tCSH
tV
HIGH IMPEDANCE
SO
tHO
VALID OUT
tDIS
HIGH IMPEDANCE
tSU
tH
SI
VALID IN
23
3387M–DFLASH–2/08
Share Link: 
