AT52BC3221AT View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT52BC3221AT' PDF : 36 Pages View PDF
AT52BC3221A(T)
PSRAM
Description
PSRAM
Features
The Pseudo-SRAM (PSRAM) is an integrated memory based on a self-refresh DRAM array.
The device is offered with density of 8-Mbit organized as 512,288 words by 16 bits. It is
designed to be identical in operation and interface to the standard 6T SRAMS. The device is
designed for low standby, low operating current and includes a user configurable low-power
mode. Two chip selects (PCS1 and ZZ) and an output enable (POE) is available to allow for
easy memory expansion. Byte controls (PUB and PLB) allow the upper and lower bytes to be
accessed independently and can also be used to deselect the device. The deep sleep mode
reduces standby current drain while not retaining data in the array.
• Fast Cycle Times
– TACC < 70 ns
• Very Low Standby Current
– ISB0 < 10 µA @ 3.0V
• Very Low Operating Current
– 1.0 mA at 3.0 and 1 µs (Typical)
• Memory Expansion with PCS1 and POE
• TTL Compatible Three-state Output Driver
Functional
Block Diagram
Row
Addresses
Clk Gen
Row
Select
Precharge Circuit
Memory Array
PVCC
PGND
3466A–STKD–11/04
I/O0 ~ I/O7
I/O8 ~ I/O15
Data
C ont
Data
C ont
Data
C ont
I/O Circuit
Column select
Column Addresses
PCS1
P OE
PWE
PUB
P LB
ZZ
Control Logic
25
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