TS8xCx2X2
are received simultaneously, an internal polling sequence determines which request is
serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
Table 12. IE Register
IE - Interrupt Enable Register (A8h)
7
6
5
4
3
2
1
0
EA
-
ET2
ES
ET1
EX1
ET0
EX0
Bit
Bit
Number Mnemonic Description
Enable All interrupt bit
Clear to disable all interrupts.
7
EA
Set to enable all interrupts.
If EA=1, each interrupt source is individually enabled or disabled by setting or
clearing its own interrupt enable bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Timer 2 overflow interrupt Enable bit
5
ET2 Clear to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
Serial port Enable bit
4
ES
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
Timer 1 overflow interrupt Enable bit
3
ET1 Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
External interrupt 1 Enable bit
2
EX1 Clear to disable external interrupt 1.
Set to enable external interrupt 1.
Timer 0 overflow interrupt Enable bit
1
ET0 Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
External interrupt 0 Enable bit
0
EX0 Clear to disable external interrupt 0.
Set to enable external interrupt 0.
Reset Value = 0X00 0000b
Bit addressable
23
4184I–8051–02/08