AT80C51RA2-3CSCV View Datasheet(PDF) - International Rectifier
Part Name
Description
MFG CO.
'AT80C51RA2-3CSCV' PDF : 85 Pages View PDF
AT/TS8xC51Rx2
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed
0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2, 3 and 4 and 5 when available: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
7. For other values, please contact your sales office.
8. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 11-5.), VIL =
VSS + 0.5 V,
VIH = VCC - 0.5V; XTAL2 N.C.; EA = Port 0 = VCC; RST = VSS. The internal ROM runs the code 80 FE (label: SJMP label). ICC
would be slightly higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is
the worst case.
Figure 11-1. ICC Test Condition, under reset
VCC
ICC
VCC
VCC
P0
VCC
RST EA
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
Figure 11-2. Operating ICC Test Condition
Reset = Vss after a high pulse
during at least 24 clock cycles
VCC
ICC
VCC
VCC
P0
RST EA
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
All other pins are disconnected.
All other pins are disconnected.
61
4188E–8051–08/06
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