Figure 11-8. External Data Memory Read Cycle
ALE
PSEN
RD
PORT 0
PORT 2
ADDRESS
OR SFR-P2
TLLDV
TWHLH
TLLWL
TRLDV
TRLRH
TLLAX
A0-A7
TAVWL
TAVDV
TRLAZ
TRHDX
DATA IN
ADDRESS A8-A15 OR SFR P2
TRHDZ
11.5.7
Serial Port Timing - Shift Register Mode
Symbol
TXLXL
TQVHX
TXHQX
TXHDX
TXHDV
Parameter
Serial port clock cycle time
Output data set-up to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
Speed
Symbol
TXLXL
TQVHX
TXHQX
TXHDX
TXHDV
Table 11-10. AC Parameters for a Fix Clock
-M
40 MHz
Min
Max
-V
X2 mode
30 MHz
60 MHz equiv.
Min
Max
-V
standard mode 40
MHz
Min
Max
-L
X2 mode
20 MHz
40 MHz equiv.
Min
Max
300
200
300
300
200
117
200
200
30
13
30
30
0
0
0
0
117
34
117
117
-L
standard mode
30 MHz
Min
Max
400
283
47
0
200
Units
ns
ns
ns
ns
ns
68 AT/TS8xC51Rx2
4188E–8051–08/06