AT88SC102-09ET-XX-2.7 View Datasheet(PDF) - Unspecified

Part Name

Description

MFG CO.

AT88SC102-09ET-XX-2.7

1K EEPROM– Security Logic with Two Application Zones

Unspecified 

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device will output a “0”.

G = On the falling edge of CLK, the address is incremented and the state of the next bit is driven on the I/O pin.

18.6 Erase Operation

Figure 18-6. Erase Operation Application Zone 1 (AZ1)

Reset

Read

Compare EZ1

(A)

Address Ax

A0

A1

A2

A431

A432 A433

A478

A479

Erase

(B)

A480

Read

(C)

(D)

A481

RST

CLK

I/O

DX

D0

D1

Output

PGM

CD432

CD433

Input

CD479

Input Output

1

Input

D480

Output

E1 flag

Notes:

1. An = Internal Address, Dn = Read data (output), CDn = Compare data (input).

2. This diagram illustrates the protocol for setting the E1 flag in Security Level 2 (issuer fuse blown). Erase operations in Secu-

rity Level 1 within Application Zone 1 do not require setting of the E1 flag. In Security Level 1, an erase operation on any bit

in Application Zone 1 will erase the entire 16-bit word containing the bit.

A = Compare sequence of EZ1. If the comparison is valid, the EZ1 flag is set to “1”, enabling erasure of AZ1.

B = If E1 is set to “1”, an erase operation on Bit 736 will erase Bits 176–687 (AZ1) (Security Level 1).

C = After the falling edge of CLK, the device will drive the I/O contact to the logic state of the existing data in Bit 736. The

state of this bit is not affected by the AZ1 erase operation.

D = After the falling edge of CLK, the address is incremented and the state of the next bit is driven on the I/O contact.

22 AT88SC102

1419C–SMEM–6/08

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