16.4 Signal Description
Figure 16-3. PSC External Block View
CLK PLL
CLK I/O
SYnIn
StopOut
12
OCRnRB[11:0]
12
OCRnSB[11:0]
12
OCRnRA[11:0]
12
OCRnSA[11:0]
4
OCRnRB[15:12]
(Flank Width
Modulation)
12
PICRn[11:0]
IRQ PSCn
AT90PWM2/3/2B/3B
PSCOUTn0
PSCOUTn1
(1)
PSCOUTn2
(1)
PSCOUTn3
PSCINn
Analog
Comparator
n Output
StopIn SYnOut PSCnASY
16.4.1
Note: 1. available only for PSC2
2. n = 0, 1 or 2
Input Description
Table 16-1. Internal Inputs
Name
Description
OCRnRB[11:0] Compare Value which Reset Signal on Part B (PSCOUTn1)
OCRnSB[11:0]
Compare Value which Set Signal on Part B (PSCOUTn1)
OCRnRA[11:0] Compare Value which Reset Signal on Part A (PSCOUTn0)
OCRnSA[11:0]
Compare Value which Set Signal on Part A (PSCOUTn0)
Type
Width
Register
12 bits
Register
12 bits
Register
12 bits
Register
12 bits
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