AT90PWM2 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT90PWM2' PDF : 365 Pages View PDF
AT90PWM2/3/2B/3B
Name
OCRnRB[15:12]
CLK I/O
CLK PLL
SYnIn
StopIn
Description
Frequency Resolution Enhancement value
(Flank Width Modulation)
Clock Input from I/O clock
Clock Input from PLL
Synchronization In (from adjacent PSC)(1)
Stop Input (for synchronized mode)
Note: 1. See Figure 16-38 on page 160
Table 16-2.
Name
PSCINn
from A C
Block Inputs
Description
Input 0 used for Retrigger or Fault functions
Input 1 used for Retrigger or Fault functions
Type
Width
Register
4 bits
Signal
Signal
Signal
Signal
Type
Width
Signal
Signal
16.4.2 Output Description
Table 16-3. Block Outputs
Name
Description
PSCOUTn0 PSC n Output 0 (from part A of PSC)
PSCOUTn1 PSC n Output 1 (from part B of PSC)
PSCOUTn2
(PSC2 only)
PSC n Output 2 (from part A or part B of PSC)
PSCOUTn3(
PSC2 only)
PSC n Output 3 (from part A or part B of PSC)
Type
Width
Signal
Signal
Signal
Signal
Table 16-4.
Name
SYnOut
PICRn
[11:0]
IRQPSCn
PSCnASY
StopOut
Internal Outputs
Description
Synchronization Output(1)
PSC n Input Capture Register
Counter value at retriggering event
PSC Interrupt Request : three souces, overflow, fault, and input
capture
ADC Synchronization (+ Amplifier Syncho. )(2)
Stop Output (for synchronized mode)
Note: 1. See Figure 16-38 on page 160
2. See “Analog Synchronization” on page 159.
Type
Width
Signal
Register
12 bits
Signal
Signal
4317K–AVR–03/2013
135
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