AT91M40400 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT91M40400' PDF : 116 Pages View PDF
AIC User Interface
Base Address: 0xFFFFF000
Table 6. AIC Memory Map
Offset
Register
0x000
Source Mode Register 0
0x004
Source Mode Register 1
–
–
0x07C
Source Mode Register 31
0x080
Source Vector Register 0
0x084
Source Vector Register 1
–
–
0x0FC
Source Vector Register 31
0x100
IRQ Vector Register
0x104
FIQ Vector Register
0x108
Interrupt Status Register
0x10C
Interrupt Pending Register
0x110
Interrupt Mask Register
0x114
Core Interrupt Status Register
0x118
Reserved
0x11C
Reserved
0x120
Interrupt Enable Command Register
0x124
Interrupt Disable Command Register
0x128
Interrupt Clear Command Register
0x12C
Interrupt Set Command Register
0x130
End of Interrupt Command Register
0x134
Spurious Vector Register
Name
AIC_SMR0
AIC_SMR1
–
AIC_SMR31
AIC_SVR0
AIC_SVR1
–
AIC_SVR31
AIC_IVR
AIC_FVR
AIC_ISR
AIC_IPR
AIC_IMR
AIC_CISR
–
–
AIC_IECR
AIC_IDCR
AIC_ICCR
AIC_ISCR
AIC_EOICR
AIC_SPU
Access
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read only
Read only
Read only
Read only
Read only
Read only
–
–
Write only
Write only
Write only
Write only
Write only
Read/Write
Reset State
0
0
0
0
0
0
0
0
0
0
0
(see Note 1)
0
0
–
–
–
–
–
–
–
0
Note: 1. The reset value of this register depends on the level of the External IRQ lines. All other sources are cleared at reset.
38
AT91M40400
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