AT91M40400 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT91M40400' PDF : 116 Pages View PDF
Standard Interrupt Sequence
It is assumed that:
• The Advanced Interrupt Controller has been
programmed, AIC_SVR are loaded with corresponding
interrupt service routine addresses and interrupts are
enabled.
• The Instruction at address 0x18(IRQ exception vector
address) is
ldr pc, [pc, #-&F20]
When NIRQ is asserted, if the bit I of CPSR is 0, the
sequence is:
1. The CPSR is stored in SPSR_irq, the current value
of the Program Counter is loaded in the IRQ link
register (r14_irq) and the Program Counter (r15) is
loaded with 0x18. In the following cycle during fetch
at address 0x1C, the ARM core adjusts r14_irq,
decrementing it by 4.
2. The ARM core enters IRQ mode, if it is not already.
3. When the instruction loaded at address 0x18 is exe-
cuted, the Program Counter is loaded with the value
read in AIC_IVR. Reading the AIC_IVR has the fol-
lowing effects:
set the current interrupt to be the pending one with the
highest priority. The current level is the priority level of
the current interrupt.
de-assert the NIRQ line on the processor. (Even if vec-
toring is not used, AIC_IVR must be read in order to
de-assert NIRQ)
automatically clear the interrupt, if it has been pro-
grammed to be edge triggered
push the current level on to the stack
return the value written in the AIC_SVR corresponding
to the current interrupt
4. The previous step has effect to branch to the corre-
sponding interrupt service routine. This should start
by saving the Link Register(r14_irq) and the
SPSR(SPSR_irq). Note that the Link Register must
be decremented by 4 when it is saved, if it is to be
restored directly into the Program Counter at the
end of the interrupt.
5. Further interrupts can then be unmasked by clear-
ing the I bit in the CPSR, allowing re-assertion of
the NIRQ to be taken into account by the core. This
can occur if an interrupt with a higher priority than
the current one occurs.
6. The Interrupt Handler can then proceed as
required, saving the registers which will be used
and restoring them at the end. During this phase, an
interrupt of priority higher than the current level will
restart the sequence from step 1. Note that if the
interrupt is programmed to be level sensitive, the
source of the interrupt must be cleared during this
phase.
7. The I bit in the CPSR must be set in order to mask
interrupts before exiting, to ensure that the interrupt
is completed in an orderly manner.
8. The End Of Interrupt Command Register
(AIC_EOICR) must be written in order to indicate to
the AIC that the current interrupt is finished. This
causes the current level to be popped from the
stack, restoring the previous current level if one
exists on the stack. If another interrupt is pending,
with lower or equal priority than old current level but
with higher priority than the new current level, the
NIRQ line is re-asserted, but the interrupt sequence
does not immediately start because the I bit is set in
the core.
9. The SPSR (SPSR_irq) is restored. Finally, the
saved value of the Link Register is restored directly
into the PC. This has effect of returning from the
interrupt to whatever was being executed before,
and of loading the CPSR with the stored SPSR,
masking or unmasking the interrupts depending on
the state saved in the SPSR (the previous state of
the ARM core).
Note: The I bit in the SPSR is significant. If it is set, it indi-
cates that the ARM core was just about to mask IRQ inter-
rupts when the mask instruction was interrupted. Hence,
when the SPSR is restored, the mask instruction is com-
pleted (IRQ is masked).
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AT91M40400
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