AT91M40400 View Datasheet(PDF) - Atmel Corporation
Part Name
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MFG CO.
'AT91M40400' PDF : 116 Pages View PDF
AT91M40400
Fast Interrupt Sequence
It is assumed that:
• The Advanced Interrupt Controller has been
programmed, AIC_SVR[0] is loaded with fast interrupt
service routine address and the fast interrupt is enabled.
• The Instruction at address 0x1C(FIQ exception vector
address) is:
• ldr pc, [pc, #-&F20].
• Nested Fast Interrupts are not needed by the user.
When NFIQ is asserted, if the bit F of CPSR is 0, the
sequence is:
1. The CPSR is stored in SPSR_fiq, the current value
of the Program Counter is loaded in the FIQ link
register (r14_fiq) and the Program Counter (r15) is
loaded with 0x1C. In the following cycle, during
fetch at address 0x20, the ARM core adjusts
r14_fiq, decrementing it by 4.
2. The ARM core enters FIQ mode.
3. When the instruction loaded at address 0x1C is
executed, the Program Counter is loaded with the
value read in AIC_FVR. Reading the AIC_FVR has
effect of automatically clearing the fast interrupt
(source 0 connected to the FIQ line), if it has been
programmed to be edge triggered. In this case only,
it de-asserts the NFIQ line on the processor.
4. The previous step has effect to branch to the corre-
sponding interrupt service routine. It is not neces-
sary to save the Link Register(r14_fiq) and the
SPSR(SPSR_fiq) if nested fast interrupts are not
needed.
5. The Interrupt Handler can then proceed as
required. It is not necessary to save registers r8 to
r13 because FIQ mode has its own dedicated regis-
ters and the user r8 to r13 are banked. The other
registers, r0 to r7, must be saved before being used,
and restored at the end (before the next step). Note
that if the fast interrupt is programmed to be level
sensitive, the source of the interrupt must be
cleared during this phase in order to de-assert the
NFIQ line.
6. Finally, the Link Register (r14_fiq) is restored into
the PC after decrementing it by 4 (with instruction
sub pc, lr, #4 for example). This has effect of return-
ing from the interrupt to whatever was being exe-
cuted before, and of loading the CPSR with the
SPSR, masking or unmasking the fast interrupt
depending on the state saved in the SPSR.
Note: The F bit in the SPSR is significant. If it is set, it indi-
cates that the ARM core was just about to mask FIQ inter-
rupts when the mask instruction was interrupted. Hence
when the SPSR is restored, the interrupted instruction is
completed (FIQ is masked).
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