AT91M40400 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT91M40400' PDF : 116 Pages View PDF
AT91M40400
PIO User Interface
PIO Base Address:0xFFFF0000
Table 8. PIO Controller Memory Map
Offset
Register
0x00
PIO Enable Register
0x04
PIO Disable Register
0x08
PIO Status Register
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
0x40
0x44
0x48
0x4C
Reserved
Output Enable Register
Output Disable Register
Output Status Register
Reserved
Input Filter Enable Register
Input Filter Disable Register
Input Filter Status Register
Reserved
Set Output Data Register
Clear Output Data Register
Output Data Status Register
Pin Data Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Interrupt Status Register
Name
PIO_PER
PIO_PDR
PIO_PSR
–
PIO_OER
PIO_ODR
PIO_OSR
–
PIO_IFER
PIO_IFDR
PIO_IFSR
–
PIO_SODR
PIO_CODR
PIO_ODSR
PIO_PDSR
PIO_IER
PIO_IDR
PIO_IMR
PIO_ISR
Access
Write only
Write only
Read only
–
Write only
Write only
Read only
–
Write only
Write only
Read only
–
Write only
Write only
Read only
Read only
Write only
Write only
Read only
Read only
Reset State
–
–
0x01FFFFFF
(see also Table 7)
–
–
–
0
–
–
–
0
–
–
–
0
(see Note 1)
–
–
0
(see Note 2)
Notes: 1. The reset value of this register depends on the level of the external pins at reset.
2. This register is cleared at reset. However, the first read of the register can give a value not equal to zero if any changes
have occurred on any pins between the reset and the read.
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