AT91SAM9263B-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT91SAM9263B-CU' PDF : 52 Pages View PDF
7.5 Master to Slave Access
In most cases, all the masters can access all the slaves. However, some paths do not make sense, for example, allowing
access from the Ethernet MAC to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and are
shown as “-” in Table 7-3.
Table 7-3. Masters to Slaves Access
Master
0
1
Slave
OHCI USB
Host
Controller
Image
Sensor
Interface
0
Internal ROM
X
X
1
Internal 80 Kbyte
SRAM
X
X
2
Internal 16 Kbyte
SRAM Bank
X
X
LCD Controller
User Interface
-
-
3
DMA Controller
User Interface
-
-
USB Host User
Interface
-
-
4
External Bus
Interface 0
X
X
5
External Bus
Interface 1
X
X
6 Peripheral Bridge
-
-
2
Two D
Graphics
Controller
X
3
DMA
Controller
X
X
X
X
X
-
-
-
-
-
-
X
X
X
X
-
X
4
Ethernet
MAC
X
X
X
-
-
-
X
X
-
5
6
LCD
Controller
Peripheral
DMA
Controller
X
X
X
X
X
X
-
-
-
-
-
-
X
X
X
X
-
X
7&8
ARM926
Data &
Instruction
X
X
X
X
X
X
X
X
X
7.6 Peripheral DMA Controller
z Acts as one Matrix Master
z Allows data transfers between a peripheral and memory without any intervention of the processor
z Next Pointer support, removes heavy real-time constraints on buffer management.
z Twenty channels
z Two for each USART
z Two for the Debug Unit
z Two for each Serial Synchronous Controller
z Two for each Serial Peripheral Interface
z Two for the AC97 Controller
z One for each Multimedia Card Interface
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (low to
high priorities):
z DBGU Transmit Channel
z USART2 Transmit Channel
z USART1 Transmit Channel
z USART0 Transmit Channel
z AC97 Transmit Channel
SAM9263 [Summary] 17
6249IS–ATARM–28-Jan-13
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