z SPI1 Transmit Channel
z SPI0 Transmit Channel
z SSC1 Transmit Channel
z SSC0 Transmit Channel
z DBGU Receive Channel
z USART2 Receive Channel
z USART1 Receive Channel
z USART0 Receive Channel
z AC97 Receive Channel
z SPI1 Receive Channel
z SPI0 Receive Channel
z SSC1 Receive Channel
z SSC0 Receive Channel
z MCI1 Transmit/Receive Channel
z MCI0 Transmit/Receive Channel
7.7 DMA Controller
z Acts as one Matrix Master
z Embeds 2 unidirectional channels with programmable priority
z Address Generation
z Source/destination address programming
z Address increment, decrement or no change
z DMA chaining support for multiple non-contiguous data blocks through use of linked lists
z Scatter support for placing fields into a system memory area from a contiguous transfer. Writing a stream of
data into non-contiguous fields in system memory.
z Gather support for extracting fields from a system memory area into a contiguous transfer
z User enabled auto-reloading of source, destination and control registers from initially programmed values at
the end of a block transfer
z Auto-loading of source, destination and control registers from system memory at end of block transfer in
block chaining mode
z Unaligned system address to data transfer width supported in hardware
z Channel Buffering
z Two 8-word FIFOs
z Automatic packing/unpacking of data to fit FIFO width
z Channel Control
z Programmable multiple transaction size for each channel
z Support for cleanly disabling a channel without data loss
z Suspend DMA operation
z Programmable DMA lock transfer support.
z Transfer Initiation
z Supports four external DMA Requests
z Support for software handshaking interface. Memory mapped registers can be used to control the flow of a
DMA transfer in place of a hardware handshaking interface
z Interrupt
z Programmable interrupt generation on DMA transfer completion, Block transfer completion, Single/Multiple
transaction completion or Error condition
SAM9263 [Summary] 18
6249IS–ATARM–28-Jan-13