11.3
CP15 Coprocessor
Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the
items in the list below:
• ARM9EJ-S
• Caches (ICache, DCache and write buffer)
• MMU
• Other system options
To control these features, CP15 provides 16 additional registers. See Table 11-5.
Table 11-5. CP15 Registers
Register
0
0
Name
ID Code(1)
Cache type(1)
1
Control
2
Translation Table Base
3
Domain Access Control
4
Reserved
5
Data fault Status(1)
5
Instruction fault status(1)
6
Fault Address
7
Cache Operations
8
TLB operations
9
Cache lockdown(2)
10
TLB lockdown
11
Reserved
12
Reserved
13
FCSE PID(1)
13
Context ID(1)
14
Reserved
15
Test configuration
Read/Write
Read/Unpredictable
Read/Unpredictable
Read/write
Read/write
Read/write
None
Read/write
Read/write
Read/write
Read/Write
Unpredictable/Write
Read/write
Read/write
None
None
Read/write
Read/Write
None
Read/Write
Notes:
1. Register locations 0, 5 and 13 each provide access to more than one register. The register
accessed depends on the value of the opcode_2 field.
2. Register location 9 provides access to more than one register. The register accessed depends
on the value of the CRm field.
46 AT91SAM9G10
6462A–ATARM–03-Jun-09