AT91SAM9G45 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT91SAM9G45' PDF : 1159 Pages View PDF
9.4.8
ARM Instruction Set Overview
The ARM instruction set is divided into:
• Branch instructions
• Data processing instructions
• Status register transfer instructions
• Load and Store instructions
• Coprocessor instructions
• Exception-generating instructions
ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]).
For further details, see the ARM Technical Reference Manual.
Table 9-2 gives the ARM instruction mnemonic list.
Table 9-2.
Mnemonic
MOV
ADD
SUB
RSB
CMP
TST
AND
EOR
MUL
SMULL
ARM Instruction Mnemonic List
Operation
Move
Add
Subtract
Reverse Subtract
Compare
Test
Logical AND
Logical Exclusive OR
Multiply
Sign Long Multiply
SMLAL
Signed Long Multiply Accumulate
MSR
B
BX
LDR
LDRSH
LDRSB
LDRH
LDRB
LDRBT
LDRT
LDM
SWP
MCR
LDC
CDP
Move to Status Register
Branch
Branch and Exchange
Load Word
Load Signed Halfword
Load Signed Byte
Load Half Word
Load Byte
Load Register Byte with
Translation
Load Register with Translation
Load Multiple
Swap Word
Move To Coprocessor
Load To Coprocessor
Coprocessor Data Processing
Mnemonic
MVN
ADC
SBC
RSC
CMN
TEQ
BIC
ORR
MLA
UMULL
UMLAL
MRS
BL
SWI
STR
STRH
STRB
STRBT
STRT
STM
SWPB
MRC
STC
Operation
Move Not
Add with Carry
Subtract with Carry
Reverse Subtract with Carry
Compare Negated
Test Equivalence
Bit Clear
Logical (inclusive) OR
Multiply Accumulate
Unsigned Long Multiply
Unsigned Long Multiply
Accumulate
Move From Status Register
Branch and Link
Software Interrupt
Store Word
Store Half Word
Store Byte
Store Register Byte with
Translation
Store Register with Translation
Store Multiple
Swap Byte
Move From Coprocessor
Store From Coprocessor
SAM9G45 [DATASHEET] 39
6438K–ATARM–12-Feb-13
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