AT91SAM9G45 View Datasheet(PDF) - Atmel Corporation
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'AT91SAM9G45' PDF : 1159 Pages View PDF
9.4.9 New ARM Instruction Set
.
Table 9-3.
Mnemonic
BXJ
New ARM Instruction Mnemonic List
Operation
Mnemonic
Branch and exchange to Java
MRRC
BLX (1)
Branch, Link and exchange
MCR2
SMLAxy
Signed Multiply Accumulate 16 *
16 bit
MCRR
SMLAL
Signed Multiply Accumulate Long
CDP2
SMLAWy
Signed Multiply Accumulate 32 *
16 bit
BKPT
SMULxy
Signed Multiply 16 * 16 bit
PLD
SMULWy
Signed Multiply 32 * 16 bit
STRD
QADD
Saturated Add
STC2
QDADD
QSUB
QDSUB
Saturated Add with Double
Saturated subtract
Saturated Subtract with double
LDRD
LDC2
CLZ
Operation
Move double from coprocessor
Alternative move of ARM reg to
coprocessor
Move double to coprocessor
Alternative Coprocessor Data
Processing
Breakpoint
Soft Preload, Memory prepare to
load from address
Store Double
Alternative Store from
Coprocessor
Load Double
Alternative Load to Coprocessor
Count Leading Zeroes
Notes: 1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
9.4.10 Thumb Instruction Set Overview
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
• Branch instructions
• Data processing instructions
• Load and Store instructions
• Load and Store multiple instructions
• Exception-generating instruction
Table 5 shows the Thumb instruction set, for further details, see the ARM Technical Reference Manual.
Table 9-4 gives the Thumb instruction mnemonic list.
Table 9-4.
Mnemonic
MOV
ADD
SUB
CMP
TST
AND
Thumb Instruction Mnemonic List
Operation
Move
Add
Subtract
Compare
Test
Logical AND
Mnemonic
MVN
ADC
SBC
CMN
NEG
BIC
Operation
Move Not
Add with Carry
Subtract with Carry
Compare Negated
Negate
Bit Clear
SAM9G45 [DATASHEET] 40
6438K–ATARM–12-Feb-13
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