Figure 5-26. Alternate Port Functions(1)
1
0
1
0
PUOExn
PUOVxn
DDOExn
DDOVxn
PUD
Q
D
DDxn
Q CLR
RESET
WDx
RDx
PVOExn
1
PVOVxn
Pnx
0
1
Q
D
0
PORTxn
DIEOExn
1
DIEOVxn
0
SLEEP
Q CLR
RESET
PTOExn
WRx
RRx
WPx
Synchronizer
D SET Q
L CLR Q
D
Q
PINxn
CLR Q
RPx
CLKI/O
DIxn
AIOxn
PUOExn:
PUOVxn:
DDOExn:
DDOVxn:
PVOExn:
PVOVxn:
DIEOExn:
DIEOVxn:
SLEEP:
PTOExn:
Pxn PULL-UP OVERRIDE ENABLE
Pxn PULL-UP OVERRIDE VALUE
Pxn DATA DIRECTION OVERRIDE ENABLE
Pxn DATA DIRECTION OVERRIDE VALUE
Pxn PORT VALUE OVERRIDE ENABLE
Pxn PORT VALUE OVERRIDE VALUE
Pxn DIGITAL INPUT ENABLE OVERRIDE ENABLE
Pxn DIGITAL INPUT ENABLE OVERRIDE VALUE
SLEEP CONTROL
Pxn, PORT TOGGLE OVERRIDE ENABLE
PUD:
WDx:
RDx:
RRx:
WRx:
RPx:
WPx:
CLK:I/O
DIxn:
AIOxn:
PULL-UP DISABLE
WRITE DDRx
READ DDRx
READ PORTx REGISTER
WRITE PORTx
READ PORTx PIN
WRITE PINx
I/O CLOCK
DIGITAL INPUT PIN n ON PORTx
ANALOG INPUT/OUTPUT PIN n ON PORTx
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD
are common to all ports. All other signals are unique for each pin.
82 ATA6612C/ATA6613C [DATASHEET]
9111L–AUTO–11/14