Table 5-40. Overriding Signals for Alternate Functions in PD3..PD0
Signal Name PD3/OC2B/INT1/PCINT19
PUOE
0
PUO
0
DDOE
0
DDOV
0
PVOE
OC2B ENABLE
PVOV
OC2B
DIEOE
INT1 ENABLE + PCINT19
× PCIE2
DIEOV
1
DI
PCINT19 INPUT
INT1 INPUT
AIO
–
PD2/INT0/PCINT18
0
0
0
0
0
0
INT0 ENABLE + PCINT18
× PCIE1
1
PCINT18 INPUT
INT0 INPUT
–
PD1/TXD/PCINT17 PD0/RXD/PCINT16
TXEN
RXEN
0
PORTD0 × PUD
TXEN
RXEN
1
0
TXEN
0
TXD
0
PCINT17 × PCIE2 PCINT16 × PCIE2
1
PCINT17 INPUT
–
1
PCINT16 INPUT
RXD
–
5.10.4 Register Description for I/O Ports
5.10.4.1 The Port B Data Register – PORTB
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
PORTB
5.10.4.2 The Port B Data Direction Register – DDRB
Bit
Read/Write
Initial Value
7
DDB7
R/W
0
6
DDB6
R/W
0
5
DDB5
R/W
0
4
DDB4
R/W
0
5.10.4.3 The Port B Input Pins Address – PINB
3
DDB3
R/W
0
2
DDB2
R/W
0
1
DDB1
R/W
0
0
DDB0
R/W
0
DDRB
Bit
Read/Write
Initial Value
7
PINB7
R
N/A
6
PINB6
R
N/A
5
PINB5
R
N/A
4
PINB4
R
N/A
3
PINB3
R
N/A
2
PINB2
R
N/A
1
PINB1
R
N/A
0
PINB0
R
N/A
PINB
5.10.4.4 The Port C Data Register – PORTC
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
–
PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
5.10.4.5 The Port C Data Direction Register – DDRC
Bit
7
–
Read/Write
R
Initial Value
0
6
DDC6
R/W
0
5
DDC5
R/W
0
4
DDC4
R/W
0
3
DDC3
R/W
0
2
DDC2
R/W
0
1
DDC1
R/W
0
0
DDC0
R/W
0
DDRC
ATA6612C/ATA6613C [DATASHEET]
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