5.12.1 Overview
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 5-27. The device-specific I/O register and bit
locations are listed in the Section 5.12.8 “8-bit Timer/Counter Register Description” on page 107.
The PRTIM0 bit in Section 5.7.7.1 “Power Reduction Register - PRR” on page 58 must be written to zero to enable
Timer/Counter0 module.
Figure 5-27. 8-bit Timer/Counter Block Diagram
Count
Clear
Direction
Timer/Counter
TCNTn
Control Logic clkTn
TOP BOTTOM
=
=0
Prescaler
TOVn (Int. Req.)
T/C
Oscillator
TOSC1
TOSC2
clkI/O
OCnA (Int. Req.)
=
Waveform
Generation
OCnA
OCRnA
=
OCRnB
Fixed
TOP
Value
OCnB (Int. Req.)
Waveform
Generation
OCnB
TCCRnA
TCCRnB
ATA6612C/ATA6613C [DATASHEET]
97
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