ATEMGA128L View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATEMGA128L' PDF : 395 Pages View PDF
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be
written to WDE even though it is set to one before the disable operation starts.
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the
Watchdog.
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algo-
rithm described above. See “Timed Sequences for Changing the Configuration of the
Watchdog Timer” on page 57.
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding
Timeout Periods are shown in Table 22.
Table 22. Watchdog Timer Prescale Select
WDP2 WDP1 WDP0
Number of WDT
Oscillator Cycles
0
0
0
16K (16,384)
0
0
1
32K (32,768)
0
1
0
64K (65,536)
0
1
1
128K (131,072)
1
0
0
256K (262,144)
1
0
1
512K (524,288)
1
1
0
1,024K (1,048,576)
1
1
1
2,048K (2,097,152)
Typical Time-out
at VCC = 3.0V
14.8 ms
29.6 ms
59.1 ms
0.12 s
0.24 s
0.47 s
0.95 s
1.9 s
Typical Time-out
at VCC = 5.0V
14.0 ms
28.1 ms
56.2 ms
0.11 s
0.22 s
0.45 s
0.9 s
1.8 s
56 ATmega128
2467O–AVR–10/06
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