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ATF-521P8-BLK View Datasheet(PDF) - Avago Technologies

Part Name
Description
MFG CO.
'ATF-521P8-BLK' PDF : 23 Pages View PDF
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ATF-521P8 Electrical Specifications
TA = 25°C, DC bias for RF parameters is Vds = 4.5V and Ids = 200 mA unless otherwise specified.
Symbol
Parameter and Test Condition
Units
Min. Typ.
Vgs
Operational Gate Voltage Vds = 4.5V, Ids = 200 mA V
0.62
Vth
Threshold Voltage Vds = 4.5V, Ids = 16 mA V
0.28
Idss
Saturated Drain Current Vds = 4.5V, Vgs = 0V
µA
14.8
Gm
Transconductance Vds = 4.5V, Gm = ∆Idss/∆Vgs;mmho —
Vgs = Vgs1 - Vgs2
Vgs1 = 0.55V, Vgs2 = 0.5V
1300
Igss
Gate Leakage Current Vds = 0V, Vgs = -4V
µA -20
0.49
NF
Noise Figure [1] f = 2 GHz
f = 900 MHz
dB ­
1.5
dB
1.2
G
Gain[1] f = 2 GHz
f = 900 MHz
dB
15.5
17
dB
17.2
OIP3
Output 3rd Order f = 2 GHz
Intercept Point[1] f = 900 MHz
dBm
38.5
42
dBm
42.5
P1dB
Output 1dB f = 2 GHz
Compressed[1] f = 900 MHz
dBm
25
26.5
dBm
26.5
PAE Power Added Efficiency
f = 2 GHz %
45
60
f = 900 MHz
%
56
ACLR
Adjacent Channel Leakage Offset BW = 5 MHz
dBc
— -51.4
Power Ratio[1,2] Offset BW = 10 MHz
dBc
— -61.5
Notes:
1. Measurements obtained using production test board described in Figure 6.
2. ACLR test spec is based on 3GPP TS 25.141 V5.3.1 (2002-06)
– Test Model 1
– Active Channels: PCCPCH + SCH + CPICH + PICH + SCCPCH + 64 DPCH (SF=128)
– Freq = 2140 MHz
– Pin = -5 dBm
– Chan Integ Bw = 3.84 MHz
Max.
18.5
Input
50 Ohm
Transmission
Line Including
Gate Bias T
(0.3 dB loss)
Input
Matching Circuit
Γ_mag = 0.55
Γ_ang = -166°
(1.1 dB loss)
Output
Matching Circuit
DUT
Γ_mag = 0.35
Γ_ang = 168°
(0.9 dB loss)
50 Ohm
Transmission
Line and
Drain Bias T
(0.3 dB loss)
Output
Figure 6. Block diagram of the 2 GHz production test board used for NF, Gain, OIP3 , P1dB and PAE and ACLR measurements. This cir-
cuit achieves a trade-off between optimal OIP3, P1dB and VSWR. Circuit losses have been de-embedded from actual measurements.

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