Active Bias[2]
Due to very high DC power
dissipation and small package
constraints, it is recommended
that ATF-521P8 use active
biasing. The main advantage of
an active biasing scheme is the
ability to hold the drain to source
current constant over a wide
range of temperature variations.
A very inexpensive method of
accomplishing this is to use two
PNP bipolar transistors arranged
in a current mirror configuration
as shown in Figure 9. Due to
resistors R1 and R3, this circuit
is not acting as a true current
mirror, but if the voltage drop
across R1 and R3 is kept identi-
cal then it still displays some of
the more useful characteristics of
a current mirror. For example,
transistor Q1 is configured with
its base and collector tied
together. This acts as a simple PN
junction, which helps tempera-
ture compensate the Emitter-
Base junction of Q2.
To calculate the values of R1, R2,
R3, and R4 the following param-
eters must be know or chosen
first:
Ids is the device drain-to-source
current;
IR is the Reference current for
active bias;
Vdd is the power supply voltage
available;
Vds is the device drain-to-source
voltage;
Vg is the typical gate bias;
Vbe1 is the typical Base-Emitter
turn on voltage for Q1 & Q2;
Therefore, resistor R3, which sets
the desired device drain current,
is calculated as follows:
R3 = Vdd – Vds
(4)
Ids + IC2 p
where,
IC2 is chosen for stability to be
10 times the typical gate current
R2
Q1 VE R1
Vdd
R4 Vg
Vds R3
C6
Q2
C4
C5
and also equal to the reference
current IR.
The next three equations are
used to calculate the rest of the
biasing resistors for Figure 9.
Note that the voltage drop across
R1 must be set equal to the
voltage drop across R3, but with
a current of IR.
R1 = Vdd – Vds
(5)
IR p
R2 sets the bias current through
Q1.
R2 = Vds – Vbe1
(6)
IR p
R4 sets the gate voltage for
ATF-521P8.
R4 = Vg
(7)
IC2 p
Thus, by forcing the emitter
voltage (VE) of transistor Q1
equal to Vds, this circuit regulates
the drain current similar to a
current mirror. As long as Q2
operates in the forward active
mode, this holds true. In other
words, the Collector-Base junc-
tion of Q2 must be kept reversed
biased.
C3
R5
R6
C8
L2
L3
RFin
C1
L1 2 2PL 7
C7
RFout
C2
ATF-521P8
L4
Figure 9. Active Bias Circuit.
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