ATF-551M4 View Datasheet(PDF) - Avago Technologies
Part Name
Description
MFG CO.
ATF-551M4
Avago Technologies
'ATF-551M4' PDF : 23 Pages View PDF
VDD is the power supply voltage.
Vds is the device drain to source voltage.
Ids is the desired drain current.
IBB is the current flowing through the R1/R2 resistor
voltage divider network.
The value of resistors R1 and R2 are calculated with the
following formulas.
R1 = Vgs
Ip
BB
(2)
R2 = (Vds – Vgs) R1
gs
(3)
Example Circuit
VDD = 3V
Vds = 2.7V
Ids = 10 mA
Vgs = 0.47V
Choose IBB to be at least 10X the maximum expected
gate leakage current. IBB was conservatively chosen to
be 0.5 mA for this example. Using equations (1), (2), and
(3) the resistors are calculated as follows
R1 = 940Ω
R2 = 4460Ω
R3 = 28.6Ω
Active Biasing
Active biasing provides a means of keeping the
quiescent bias point constant over temperature and
constant over lot to lot variations in device dc perfor-
mance. The advantage of the active biasing of an en-
hancement mode PHEMT versus a depletion mode
PHEMT is that a negative power source is not required.
INPUT
Zo
C1
Q1
L1
L2
C2
R5
C3
R6
C7
Q2
R7
R1
C4
OUTPUT
Zo
L4
L3
C5
R4
C6
Vdd
R3
R2
Figure 38. Typical ATF-551M4 LNA with Active Biasing.
The techniques of active biasing an enhancement
mode device are very similar to those used to bias a
bipolar junction transistor. An active bias scheme is
shown in Figure 38.
R1 and R2 provide a constant voltage source at the
base of a PNP transistor at Q2. The constant voltage
at the base of Q2 is raised by 0.7 volts at the emitter.
The constant emitter voltage plus the regulated VDD
supply are present across resistor R3. Constant voltage
across R3 provides a constant current supply for the
drain current. Resistors R1 and R2 are used to set the
desired Vds. The combined series value of these resistors
also sets the amount of extra current consumed by the
bias network. The equations that describe the circuit’s
operation are as follows.
VE = Vds + (Ids • R4) (1)
R3 = VDD – VE
(2)
Ip
ds
VB = VE – VBE
(3)
VB = R1 VDD (4)
R1 + R2p
VDD = IBB (R1 + R2) (5)
Rearranging equation (4)provides the following formula
R2 = R 1 (VDD – VB) (4A)
VB
p
and rearranging equation (5) provides the follow
formula
R1 =
VDD
(5A)
( ) IBB
1
+
V
DD –
VB
VBp
9
Example Circuit
VDD = 3 V, Vds = 2.7 V, Ids = 10 mA, R4 = 10Ω, VBE = 0.7 V
Equation (1) calculates the required voltage at the
emitter of the PNP transistor based on desired Vds and
Ids through resistor R4 to be 2.8V. Equation (2) calcu-
lates the value of resistor R3 which determines the
drain current Ids. In the example R3=18.2Ω. Equation
(3) calculates the voltage required at the junction of
resistors R1 and R2. This voltage plus the step-up of
the base emitter junction determines the regulated
Vds. Equations (4) and (5) are solved simultaneously
to determine the value of resistors R1 and R2. In the
example R1=4200Ω and R2 =1800Ω.
20
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