ATMEGA128L-8MC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATMEGA128L-8MC' PDF : 395 Pages View PDF
ATmega128
Each half period of the external clock applied must be longer than one system clock
cycle to ensure correct sampling. The external clock must be guaranteed to have less
than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since
the edge detector uses sampling, the maximum frequency of an external clock it can
detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari-
ation of the system clock frequency and duty cycle caused by Oscillator source (crystal,
resonator, and capacitors) tolerances, it is recommended that maximum frequency of an
external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 60. Prescaler for Timer/Counter1, Timer/Counter2, and Timer/Counter3
CK
10-BIT T/C PRESCALER
Clear
PSR321
T3
0
CS30
CS31
CS32
T2
0
CS20
CS21
CS22
T1
0
CS10
CS11
CS12
TIMER/COUNTER3 CLOCK SOURCE
clkT3
TIMER/COUNTER2 CLOCK SOURCE
clkT2
TIMER/COUNTER1 CLOCK SOURCE
clkT1
Note: The synchronization logic on the input pins (T3/T2/T1) is shown in Figure 59.
Special Function IO Register –
SFIOR
Bit
7
6
5
4
3
2
1
0
TSM
–
–
–
ACME
PUD
PSR0 PSR321 SFIOR
Read/Write
R/W
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this
mode, the value that is written to the PSR0 and PSR321 bits is kept, hence keeping the
corresponding prescaler reset signals asserted. This ensures that the corresponding
Timer/Counters are halted and can be configured to the same value without the risk of
one of them advancing during configuration. When the TSM bit is written to zero, the
PSR0 and PSR321 bits are cleared by hardware, and the Timer/Counters start counting
simultaneously.
• Bit 0 – PSR321: Prescaler Reset Timer/Counter3, Timer/Counter2, and
Timer/Counter1
When this bit is one, the Timer/Counter3, Timer/Counter1, and Timer/Counter2 pres-
caler will be reset. This bit is normally cleared immediately by hardware, except if the
TSM bit is set. Note that Timer/Counter3, Timer/Counter1, and Timer/Counter2 share
the same prescaler and a reset of this prescaler will affect all three timers.
2467O–AVR–10/06
145
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