ATMEGA128L-8MC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATMEGA128L-8MC' PDF : 395 Pages View PDF
Compare Match Output
Unit
put Compare (FOC2) strobe bits in normal mode. The OC2 Register keeps its value
even when changing between waveform generation modes.
Be aware that the COM21:0 bits are not double buffered together with the compare
value. Changing the COM21:0 bits will take effect immediately.
The Compare Output mode (COM21:0) bits have two functions. The waveform genera-
tor uses the COM21:0 bits for defining the output compare (OC2) state at the next
compare match. Also, the COM21:0 bits control the OC2 pin output source. Figure 64
shows a simplified schematic of the logic affected by the COM21:0 bit setting. The I/O
registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the gen-
eral I/O Port Control Registers (DDR and PORT) that are affected by the COM21:0 bits
are shown. When referring to the OC2 state, the reference is for the internal OC2 Regis-
ter, not the OC2 pin. If a System Reset occur, the OC2 Register is reset to “0”.
Figure 64. Compare Match Output Unit, Schematic
COMn1
COMn0
FOCn
Waveform
Generator
DQ
1
OCn
OCn
Pin
0
DQ
PORT
DQ
Compare Output Mode and
Waveform Generation
clkI/O
DDR
The general I/O port function is overridden by the output compare (OC2) from the wave-
form generator if either of the COM21:0 bits are set. However, the OC2 pin direction
(input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
The Data Direction Register bit for the OC2 pin (DDR_OC2) must be set as output
before the OC2 value is visible on the pin. The port override function is independent of
the Waveform Generation mode.
The design of the output compare pin logic allows initialization of the OC2 state before
the output is enabled. Note that some COM21:0 bit settings are reserved for certain
modes of operation. See “8-bit Timer/Counter Register Description” on page 158.
The waveform generator uses the COM21:0 bits differently in normal, CTC, and PWM
modes. For all modes, setting the COM21:0 = 0 tells the waveform generator that no
action on the OC2 Register is to be performed on the next compare match. For compare
output actions in the non-PWM modes refer to Table 65 on page 159. For fast PWM
mode, refer to Table 66 on page 159, and for phase correct PWM refer to Table 67 on
page 159.
150 ATmega128
2467O–AVR–10/06
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